1. Field of the Invention
The present invention relates to a semiconductor memory. More specifically, it relates to a semiconductor memory having source line contacts CS and bit line contacts CB, and a fabrication method for the same.
2. Related Art
Conventionally, a NAND flash EEPROM is known as an electrically erasable and highly integratable nonvolatile semiconductor memory. A NAND flash EEPROM memory cell transistor has a stacked gate structure where a floating gate electrode layer or a floating gate electrode film, which is for charge accumulation, and a control gate electrode are stacked on a semiconductor substrate via an insulating film layer. A NAND cell unit is configured by vertically connecting multiple memory cell transistors in series such that neighboring memory cell transistors share either a common source or a common drain region, and arranging select gate transistors at both sides thereof.
A memory cell array is configured by arranging NAND cell units in a matrix. NAND cell units arranged in a row are called a ‘NAND cell block’. The gates of select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of memory cell transistors arranged in the same row are connected to the same control gate line.
A contact for connecting a bit line and a source line is formed at both sides of each NAND cell unit, allowing an electric current to flow through each NAND cell unit. An arrangement such that two adjacent NAND cell units share a single contact is typically used for reducing the area occupied by the contacts. Accordingly, a NAND cell unit is symmetrically arranged with bit line contacts CB and source line contacts CS as points of symmetry. Each of the bit line contacts CB and the source line contacts CS is formed between corresponding select gate transistors of adjacent NAND cell units.
The NAND cell units are vertically arranged at equal intervals. In other words, widths of all regions in which contacts are to be formed within a cell array are equal. With this structure, voids, which are parallel to select gate lines, are formed in the regions in which contacts are to be formed so that the aspect ratio before embedding an interlayer insulating film is large. In the case where the bit line contacts CB are formed therein, there is a high probability of a bit line BL short occurring due to contact plug material wrap-around.
Japanese Patent Application Laid-open No. 2001-196482 relates to a flash memory that is formed by applying a local interconnection to the source line and discloses a method of monitoring whether or not a source contact with a narrow contact area has been in contact with an electrode by utilizing properties of an over erased cell of a flash.
Japanese Patent Application Laid-open No. Hei 03-283662 discloses a structure of a NAND EEPROM, which improves bit line contact yield and area reduction by using an extended electrode for the bit line contact. Cost is reduced by decreasing the number of processes, see FIG. 4 of Japanese Patent Application Laid-open No. Hei 03-283662.
With a flash memory semiconductor device having a multi-level interconnect structure where voids are formed in interlayer insulating films so as to reduce the parasitic capacitance between interconnects, there is a disadvantage of short circuiting adjacent bit lines via a metal that has penetrated into inter-contact voids when the contacts extend over the voids formed between word lines. Consequently, as a void countermeasure, a structure of a semiconductor device allows formation of inter-bit line contacts and diffusion layers on the interlayer insulating films so as to intersect with voids by forming a sidewall insulating film such as a nitride film on the inner wall of the contact. This structure also prevents short circuits through the inter-bit line contacts; and reduces the parasitic capacitance between word lines (See Japanese Patent Application Laid-open No. 2002-1100791).
A requirement for embedding an interlayer insulating film is to avoid generating voids and/or seams in the regions in which contacts are to be formed. Assuming that voids and/or seams exist, deposition of contact plugs through a film formation method with excellent step coverage such as CVD increases a possibility of short circuiting the bit lines BL due to the material of the contact plugs penetrating into the void and/or seam interiors In actuality, a BPSG film with excellent reflow characteristics after deposition thereof also often includes voids or seams. Consequently, embedding the voids and/or seams in a subsequent reflow step avoids void embedding. However, avoids void embedding is recently becoming more difficult due to the following factors.
Firstly, the greater the down-scaling, the narrower the spaces between select gate transistors, while the heights of gate electrodes are less scaled down. As a result, the aspect ratio before embedding an interlayer insulating film increases from generation to generation, and voids become easier to generate.
Secondly, there is a need for a low heat process after diffusion layer formation. The short channel effect is noticeable when the gate length is scaled down. As a result, it is necessary to control dopant impurity diffusion using a low heat process. In addition, there is a recent tendency to use a salicide film for reducing the control gate line sheet resistance A heat process of approximately 700° C. or greater after salicide film formation creates about high resistance, which does not allow use of the reflow characteristics of the interlayer insulating film. As a result, the generated voids remain.
As described thus far, avoiding void or seam generation in regions in which contacts are to be formed is an extremely significant objective for future miniaturization.
In the above description, a NAND flash EEPROM has been described as an exemplary MOS semiconductor memory; however, even a memory with another operating structure such as an AND type, NOR type, two-transistor/cell type, or three-transistor/cell type having circuitry in which bit line contacts CB are arranged in a row, avoiding void or seam generation in regions in which contacts are to be formed is also an extremely significant objective for future miniaturization.